1. Field of the Invention
The invention relates to a process for packaging components and to a component packaged in this way in general, and to a wafer level packaging process and a component packaged in this way in particular.
2. Description of Related Art
For many technical applications, there is a need for hermetically packaged chips, since it is in this way possible, for example, to protect the sensitive integrated circuits on a semiconductor substrate. However, the packaging is at least equally important for optical or micro-mechanical components.
There are known processes in which the chips are first of all divided from the wafer assembly and then packaged individually. This is an extremely complex process which is scarcely suitable for the mass production of sensitive components. In particular, the integrated circuits or other components are not (yet) protected when they are being divided from the wafer, and consequently they can become soiled and/or be destroyed during the sawing operation.
There are also known processes in which the components are first of all packaged at wafer level and then divided. These processes are known as wafer level packaging (WLP).
The prior art disclosed a number of such processes.
However, with wafer level packaging it is difficult to contact-connect the integrated circuits, since any connection contacts are typically covered by a covering substrate. This will be illustrated on the basis of the process described below.
The known processes generally work on the assumption that the connections to the contact regions on the chips or at the integrated circuits can be produced directly, as can be achieved without problems, for example, in the case of memory chips.
However, this takes no account of the fact that, for example in the case of chips with an integrated sensor or optical component, the optically active surface in the mounted state, for example on a printed circuit board, has to remain uncovered.
In this respect, WO 99/40624 has disclosed a process in which it is attempted to eliminate the problems outlined above by the connection contacts which are present at the active component being routed from the active side onto the opposite underside of the wafer or chip. The further contact-connection of the connection contacts routed downwards can then be carried out in a known way.
Moreover, a similar process is described in “Wafer Level Chip Scale Packaging: Benefits for Integrated Passive Devices”, Clearfield, H. M.; Young, J. L.; Wijeyesekera, S. D.; Logan, E. A.; IEEE Transactions on Advanced Packaging, Vol. 23, No. 2, pages 247-251.
The abovementioned process is distinguished by the fact that, after a glass covering has been applied to the optically active front surface of a wafer, trenches which divide the wafer into individual chip regions are produced along the underside of the wafer. During the production of the trenches, the connection contact locations located on the active side of the wafer, in each case on the transition region between two chips, are divided and thereby uncovered in the trenches. To completely package the wafer or chips, after the trenches have been produced, a piece of glass is adhesively bonded over the trenches and is then cut into in a suitable way such that the trenches in the wafer and the connection contact locations are once again freely accessible. This is followed by deposition of contact tracks in the trenches which have been produced, which is intended to effect contact-connection of the connection contact locations and to lay the contact location onto the back surface of the packaged chip.
Although the proposed process leads to what is known as through-contacting of the connection contacts from the active front surface of the chip or wafer to the passive back surface, this gives rise to a number of significant drawbacks, making chips which have been produced using the process under discussion disproportionately expensive.
One reason for this is the fact that the trenches which are to be produced in the known process are significantly wider than those which would be considered standard for normal dicing of a wafer. The result of this is that the distances between the chips or the integrated circuits have to be relatively great, and consequently there is space for fewer chips on a wafer.
If only for this reason, the known process already gives a relatively low chip yield from a semiconductor wafer. Furthermore, the proposed production process is also relatively slow. This is related in particular to the fact that the trenches have to be ground in sequentially and also that what is known as the dicing saw can only operate at a relatively slow advance rate during production of the trenches. Apart from all this, the wear to the saw blades is also high. The dicing saws which have to be used, for this reason and on account of the high demands imposed on the dimensional accuracy of the mechanical process described and also the considerable machine costs, are very expensive.
One significant problem of the process described in WO 99/40624 is also that the uncovering of the connection contacts when grinding the trenches is effected by a dicing operation. Dicing of the connection contacts of this type, as has been mentioned above, requires an extremely high dimensional accuracy, since otherwise at least part of the contact can be destroyed. However, even if accurate cutting of the connection contact is achieved, it is not easy to produce a contact connection using the connection contacts which have been uncovered in this way. The reasons for this are in particular that the contact-connection according to the prior art is to be effected by deposition of contact tracks on the oblique walls of the trenches in the wafer, but uniform and therefore targeted deposition is only possible at a steep to perpendicular angle to the deposition direction.
When sawing along the contacts, a further particular drawback is that a number of interfaces are at least temporarily uncovered, which can lead to corrosion and diffusion and can therefore have a significant adverse effect on the service life of the components.
Further processes for the through-contacting of chips are also described in “Future Systems-on-Silicon LSI Chips”, Koyanagi, M; Kurino, H; Lee, K. W.; Sakuma, K., IEEE Micro, July-August 1998, pages 17-22, WO 98/52225 and DE 197 46 641. However, these processes are not suitable for the packaging of, for example, optical chips.
A further improved wafer level packaging process is known from WO 03/019653 A2, which is hereby incorporated in its entirety by reference in the subject matter of the present disclosure.
In the process described in that document, the contacts, after packaging, are made accessible again through passages through which the contacts are then contact-connected, for example by means of what are known as ball grid arrays. The drawbacks described above can be substantially avoided in this process.
Nevertheless, under certain circumstances a problem may be presented by the fact that the ball grid arrays generally contain a lead-tin solder, the melting point of which is approximately 230° C., and consequently the thermal stability of a chip produced in this way is insufficient for certain applications, or sensitive components are subject to excessive thermal loading during mounting. Furthermore, thermomechanical coupling between the connections with ball grid array and the semiconductor components can lead to problems in sensitive components.
In any case, under certain circumstances it is desirable to be able to make do without lead-containing solder.
Furthermore, it is desirable for the efficiency and yield of the processes described to be improved further and for the range of applications for the chips produced to be widened.